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fet input analog front end with adc driver data sheet ADA4350 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 C 2016 analog devices, inc. all rights reserved. technical support www.analog.com features low noise, low input bias current fet input amplifier very low input bias current : 0. 2 5 pa t ypical at 25c low input voltage noise 9 2 nv/hz typical at 10 hz at 5 v 5 nv/hz typical at 100 khz at 5 v gain bandwidth p roduct: 1 75 mhz input c apacitance 3 p f typical, d ifferential mode 2 pf typical, c ommon mode integrated gain switching sampling and feedback switch off leakage : 0. 5 pa t ypical worst case t on /t off time s : 105 ns typical/65 ns typical integrated analog - to - digital converter ( adc ) d river differential mode and s ingle - ended m ode adjustable output common - mode voltage ? 5 v to + 3. 8 v t ypical for 5 v supply wide o utput voltage swing: 4.8 v minimum for 5 v supply linear o utput current : 18 ma rms t ypical for 5 v supply spi or parallel switch control of all f unctions wide operating range: 3.3 v to 12 v quiescent current: 8.5 ma t ypical ( 5 v full system ) applications current to v oltage (i to v) c onversion s photo d iode p reamp lifier s chemical a nalyzers mass s pectrometry molecular s pectroscopy laser/led r eceivers data acquisition syst ems general description t he ada4 350 is an analog front end for photodetectors or other sensors whose output produces a current proportional to the s ensed parameter or voltage input applications where the system requires the user to select between very precise gain levels to maximize the dynamic range. the ada4 350 integrates a fet input amplifier, a switching network, and an adc driver with all functions controllable via a serial peripheral interface ( spi ) or parallel control logic into a single ic. the fet input amplifier has very low voltage noise and current noise making it a n excellent choice to work with a wide range of photodetectors , sensors, or precision data acquisition systems. its switching network allows the user individual selection of u p to six different, externally configurable feedback networks; by using external components for the feedback network , the user can more easily match the system to their desired photodetector or s ensor capacitance. this feature also allows the use of low th ermal drift resistors , if required. the design of the switches minimizes error sources so that they add virtually no error in the signal path. the output driver can be used in either single - ended or a differential mode and is ideal for driving the input of an adc . the ada4 350 can operate from a single +3.3 v supply or a dual 5 v supply, offering user flexibility when choosing the polarity of the detector. it is available in a pb - free, 28 - lead ts sop package and is specified to operate over the ? 40 c to +85c temperature range . multifunction pin names may be referenced by their relevant function only. functional block diagram vout2 adc driver switching network fet am p sw a_out ref in- p sw a_in en mode fb2 fb1 la tch/p0 sclk/p1 fb4 fb3 sdi/p3 vin1 rf1 swb_out vout1 spi inter f ace swb_in fb0 sdo/p2 fb5 in-n ADA4350 3 26 25 23 2 28 1 27 4 5 6 7 8 9 22 21 20 19 17 16 13 12 11 10 12417-001 s0 s1 s2 s6 s7 s8 s3 s4 s5 s9 s10 s1 1 m1 p1 cs/p4 figure 1.
ADA4350* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ADA4350 evaluation board documentation data sheet ? ADA4350: fet input analog front end with adc driver data sheet user guides ? ug-655: evaluating the ADA4350, a fet input analog front end with adc driver offered in a 28-lead 9.8 mm 6.4 mm tssop tools and simulations ? ADA4350 spice macro-model reference materials press ? integrated analog front-end simplifies sensor interfaces design resources ? ADA4350 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ADA4350 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ADA4350 data sheet rev. b | page 2 of 37 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revi sion history ............................................................................... 2 specifications ..................................................................................... 3 5 v full system ........................................................................... 3 5 v fet input amplifier ........................................................... 4 5 v internal switching network and digital pins ................. 5 5 v adc driver ......................................................................... 6 5 v full system ............................................................................. 8 5 v fet input amplifier ............................................................. 9 5 v in ternal switching network and digital pins .................. 10 5 v adc driver .......................................................................... 11 timing specifications ................................................................ 13 absolute maximum ratings .......................................................... 15 ther mal resistance .................................................................... 15 maximum power dissipation ................................................... 15 esd caution ................................................................................ 15 pin configuration and function descriptions ........................... 16 typical performance characterisitics .......................................... 17 full system .................................................................................. 17 fet input amplifier .................................................................. 19 adc driv er ................................................................................. 22 test circuits ..................................................................................... 26 theory of operation ...................................................................... 27 kelvin switching techniques .................................................... 27 applications information .............................................................. 28 configuring the ada4 350 .......................................................... 28 selecting the transimpedance gain paths manually or through the parallel interface .................................................. 28 selecting the transimpedance gain paths through the spi interface (serial mode) ....................................................... 28 spice model ............................................................................... 30 transimpedance amplifier design theory ................................ 32 transimpedance gain amplifier performance ...................... 34 the effect of low feedback resistor r fx ................................ 35 using the t network to implement large feedback resistor values ............................................................................ 36 outline dimensions ....................................................................... 37 ordering guide .......................................................................... 37 revision history 3 /16 rev. a to rev. b change to table 15 ......................................................................... 29 1 2 /15 rev. 0 to rev. a changes to table 1 ............................................................................ 3 changes to table 5 ............................................................................ 8 deleted figure 4; renumbered sequentially ............................... 14 changes to table 10 ........................................................................ 15 changes to table 14 ........................................................................ 29 4 / 1 5 rev ision 0 : initial version
data sheet ADA4350 rev. b | page 3 of 37 specifications 5 v full syste m t a = 25 c, +v s = + 5 v, ? v s = ?5 v , r l = 1 k ? differential , unless otherwise specified. table 1 . parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth g ain (g) = ? 5 , v out = 200 mv p -p 20 mhz g = ?5, v out = 2 v p -p 12 mhz slew rate v out = 2 v step , 10% to 90% 60 v/ s harmonic performance harmonic distortion (hd2/hd3) g = ? 5 , f c = 100 khz ? 95/ ? 104 dbc g = ? 5, f c = 1 mhz ? 77/ ? 78 dbc dc performance input bias c urrent at 25 c 0.25 1 pa at 8 5c 8 25 pa input characteristics input resistance common mode 1 00 g? input capacitance common mode 2 pf differential mode 3 pf input common - mode voltage range common - mode rejection ratio ( cmrr ) > 80 db ?4.5 +3.8 v cmrr > 68 db ?5 +3.9 v common - mode rejection v cm = 3 .0 v 92 104 db output characteristics linear output current v out = 4 v p - p, 60 db spurious - free dynamic range ( sfdr ) 18 ma rms short - circuit current sinking/sourcing 43/7 6 ma settling t ime to 0.1% g = ? 5, v out = 2 v step 100 ns analog power supply (+v s , ?v s ) operating range 3.3 12 v quiescent current enabled 8.5 10 ma m1 d isabled (see figure 1 ) 7 ma all d isabled 2 a positive power supply rejection ratio 90 db negative power supply rejection ratio 85 db digital supplies dvdd, dgnd digital supply range 3.3 5.5 v quiescent current enabled 50 a disabled 0.6 a +v s to dgnd head room 3.3 v
ADA4350 data sheet rev. b | page 4 of 37 5 v fet input ampli fier t a = 25c, +v s = + 5 v, ? v s = ?5 v , r l = 1 k ? , unless otherwise specified. table 2 . parameter test conditions /comments min typ max unit dynamic performance ?3 db bandwidth g = ?5, v out = 100 mv p -p 2 6 mhz g = ?5, v out = 2 v p -p 2 4 mhz gain bandwidth product 175 mhz slew rate v out = 2 v step, 10% to 90% 100 v/s settling time to 0.1% g = ? 5, v out = 2 v step 28 ns noise/ harmonic performance harmonic distortion (hd2/hd3) f = 100 khz, v out = 2 v p - p, g = ? 5 ? 106/ ? 11 4 dbc f = 1 mhz, v out = 2 v p - p, g = ? 5 ? 83 / ? 9 3 dbc input voltage noise f = 10 hz 85 nv/hz f = 100 khz 5 nv/hz dc performance input offset voltage 15 80 v input offset voltage drift from ? 40 c to + 85c 0.1 1.6 v/c from 25c to 85c 0.1 1.0 v/c input bias current at 25c 0.25 1 pa at 85c 8 25 pa input bias offset current at 25c 0. 1 0.8 pa at 85c 0.5 pa open - loop gain v out = 2 v 106 115 db input characteristics input resistance common mode 1 00 g? input capacitance common mode 2 pf differential mode 3 pf input common - mode voltage range cmrr > 80 db ?4.5 +3.8 v cmrr > 68 db ?5 +3.9 v common - mode rejection ratio v cm = 3 v 92 115 v output characteristics output overdrive recovery time v out = v s 10% 60 ns output voltage swing g = +21 , r f = 1 k? , r l open measured at fbx ? 3 .6 to + 3.9 ? 4.05 to + 4.07 v g = +21, r f = 100 k? , r l open measured at fbx ? 4.7 to + 4.8 ? 4.9 to + 4.86 v linear output current v out = 2 v p - p, 60 db sfdr 18 ma rms short - circuit current sinking/sourcing 41/45 ma power supply operating range 3.3 12 v positive power supply rejection ratio 90 109 db negative power supply rejection ratio 90 1 0 9 db
data sheet ADA4350 rev. b | page 5 of 37 5 v internal switch ing network and digital p ins t a = 25c, +v s = + 5 v, ? v s = ?5 v , unless otherwise specified . see figure 1 for feedback and sampling switches notation. table 3 . parameter symbol test conditions/comments min typ max unit feedback/sample analog switch analog signal range ? 5 + 5 v switch on - resistance feedback r on, fb for s0 to s2 , v cm = 0 v 149 196 ? t a = 8 5 c 195 ? for s3 to s5 , v cm = 0 v 1 49 196 ? t a = 8 5c 195 ? sampling r on, s for s6 to s8 , v cm = 0 v 297 356 ? t a = 8 5c 390 ? for s9 to s11 , v cm = 0 v 297 356 ? t a = 8 5c 388 ? on - resistance match between channels feedback resistance r on, fb v cm = 0 v 2 15 ? sampling resistance r on, s v cm = 0 v 2 14 ? switch leakage currents sampling and feedback switch off leakage i s (off) 0.5 1. 7 pa t a = 85c 40 120 pa dynamic characteristics power - on time t on dvdd = 5 v 76 ns dvdd = 3.3 v 80 ns power - off time t off dvdd = 5 v 86 n s dvdd = 3.3 v 90 ns off isolation r l = 50 ? , f = 1 mhz feedback switches ?92 db sampling switches ?118 db channel to channel crosstalk r l = 50 ? , f = 1 mhz ?86 db worst case switch feedback capacitance (switch off ) c fb (off) 0.1 pf threshold voltages for digital input pins en, mode, dgnd, latch /p0, s clk/p1, sdo/p2, sdi/p3, cs /p4 1 input high voltage v ih dvdd = 5 v 2.0 v dvdd = 3.3 v 1.5 v input low voltage v il dvdd = 5 v 1.4 v dvdd = 3.3 v 1.0 v digital supplies dvdd, dgnd digital supply range 3.3 5.5 v quiescent current e nabled 50 a d isabled 0.6 a +v s to dgnd h ead r oom 3.3 v 1 when referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specific ation is listed. for full pin names of multifunction pins, refer to the pin configuration and function descriptions section.
ADA4350 data sheet rev. b | page 6 of 37 5 v adc driver t a = 25c, +v s = + 5 v, ? v s = ?5 v , unless otherwise specified . see figure 1 for the p1 and m1 amplifier s. r l = 1 k ? when differential, and r l = 500 ? when single - ended. table 4 . parameter test conditions /comments 1 min typ max unit dynamic performance ?3 db bandwidth when used differentially, v out = 0.1 v p -p 38 mhz when used differentially, v o ut = 2.0 v p -p 16 mhz when p1 is used, v out = 50 m v p - p 55 mhz when p1 is used, v out = 1 .0 v p -p 17 mhz when m1 is used, v out = 50 m v p -p 45 mhz when m1 is used, v out = 1 .0 v p - p 21 mhz overdrive recovery time positive r ecover y / negative r ecovery for p1 200/180 n s positive recovery/negative recovery for m1 100/100 ns slew rate when differentially used , v out = 2 v step 57 v/s when p1 or m1 is single - ended, v out = 1 v step 30 v/s settling time 0.1 % when used differentially, v out = 2 v step 95 n s when p1 is used, v out = 1 v step 80 ns when m1 is used, v out = 1 v step 80 ns noise/distortion performance harmonic distortion ( hd2/hd3) when used differentially, f c = 100 khz, v out = 4 v p - p ? 105/ ? 109 dbc when used differentially, f c = 1 m hz, v out = 4 v p -p ? 75/ ? 7 3 dbc when p1 is used, f c = 100 k hz, v out = 2 v p -p ? 112/ ? 108 dbc when p1 is used, f c = 1 mhz, v out = 2 v p -p ? 75/ ? 7 3 dbc when m1 is used, f c = 100 khz, v out = 2 v p - p ? 98/ ? 103 dbc when m1 is used, f c = 1 mhz, v out = 2 v p -p ? 70/ ? 69 dbc referred to input (rti ) voltage noise for p1, f = 10 hz 55 nv/hz for p1, f = 100 khz 5 nv/hz referred to output (rto ) voltage noise for p1 and m1 , f = 10 hz , measured at v out 2 95 nv/hz for p1 and m1 , f = 100 khz , measured at vout2 16 nv/hz input current noise f = 100 khz , referred to p1 1.1 pa/hz dc performance output offset voltage differential 0.125 0.5 mv output offset voltage drift differential 0.7 13 v/c input offset voltage single - ended, p1 only 50 180 v single - ended, m1 only 40 180 v input offset voltage drift singl e - ended, p1 only 0.2 4.75 v/c s ingle - ended, m1 only 0.4 3.6 v/c input bias current p1 only at vin1 pin 60 220 na p1 only at rf1 pin 60 325 na m1 at ref pin 6 0 200 na input offset current p1 only 60 260 n a open - loop gain p1 only , v out = 2 v 102 112 db gain m1 only 1.99 1.9996 2.01 v/v gain error ? 0.5 + 0.5 % gain error drift 0.6 1.9 ppm /c input characteristics input resistance vin1 and ref 2 00 m? input capacitance vin1 and ref 1.4 pf input common - mode voltage range ?5 +3.8 v common - mode rejection ratio for p 1 , v cm = 3.0 v 82 100 db
data sheet ADA4350 rev. b | page 7 of 37 parameter test conditions /comments 1 min typ max unit output characteristics output voltage swing r l = no load, single - ended 4.8 4.83 v r l = 500 ? , single - ended 4.55 4.6 v output common - mode voltage range ?5 +3.8 v linear output current p1 or m1, v out = 2 v p - p, 60 db sfdr 18 ma rms differential output , v out = 4 v p - p, 60 db sfdr 18 ma rms short circuit current p1 or m1, sinking/sourcing 4 3/76 ma capacitive load drive when used differentially at each v out x , 30% overshoot, v out = 200 mv p - p 33 pf when p1/m1 is used, 30% overshoot, v out = 100 mv p - p 47 pf power supply operating range 3.3 12 v positive power supply rejection ratio for p1 90 106 db for m1 8 6 100 db negative power supply rejection ratio for p1 80 100 db for m1 78 90 db 1 p1 and m1 within this table refer to the amplifiers shown in figure 1 .
ADA4350 data sheet rev. b | page 8 of 37 5 v full system t a = 25c, +v s = 5 v, ? v s = 0 v , r f = 1 k ? differential , unless otherwise specified. table 5 . parameter test conditions /comments min typ max unit dynamic performance ?3 db bandwidth g = ?5, v out = 200 mv p -p 1 5 mhz g = ?5, v out = 1 v p -p 1 4 mhz slew rate v out = 2 v step, 10% to 90% 30 v/s h armonic performance harmonic distortion (hd2/hd3) g = ?5 , f c = 100 khz ? 85/ ? 94 dbc g = ?5, f c = 1 mhz ?66/?75 dbc input voltage noise f = 10 hz 92 nv/hz f = 100 khz 4.4 nv/hz dc performance input bias current at 25c 0.3 5 1.6 pa at 8 5c 8.5 30 pa input characteristics input resistance common mode 1 00 g? input capacitance common mode 2 pf differential mode 3 pf input common - mode voltage range cmrr > 80 db 0.5 3.8 v cmrr > 68 db 0 3.9 v common - mode rejection v cm = 0.5 v 88 94 db output characteristics linear output current v out = 1 v p - p, 60 db sfdr 9 ma rms short - circuit current sinking/sourcing, r l < 1 ? 41/63 ma settling time to 0.1% g = ?5, v out = 2 v step 130 ns power supply operating range 3.3 12 v quiescent current enabled 8 9 ma m1 disabled (see figure 1 ) 6.5 ma all disabled 2 a positive power supply rejection ratio 86 db negative power supply rejection ratio 80 db digital supplies (dvdd, dgnd) dvdd, dgnd digital supply range 3.3 5.5 v quiescent current enabled 50 a disabled 0.6 a +v s to dgnd head room 3.3 v
data sheet ADA4350 rev. b | page 9 of 37 5 v fet input amplif ier t a = 25 c, +v s = 5 v, ? v s = 0 v , r l = 1 k ? , unless otherwise specified. table 6 . parameter test conditions/comments min typ max unit dynamic performance ?3 db bandwidth g = ?5, v out = 100 mv p -p 2 5 mhz g = ?5, v out = 1 v p -p 2 4 mhz gain bandwidth product 175 mhz slew rate v out = 2 v step, 10% to 90% 56 v/s settling time to 0.1% g = ? 5, v out = 2 v step 60 ns noise/harmonic performance harmonic distortion (hd2/hd3) f = 100 khz, v out = 1 v p - p, g = ? 5 ? 113/ ? 1 17 dbc f = 1 mhz, v out = 1 v p - p, g = ? 5 ? 82/ ? 8 3 dbc input voltage noise f = 10 hz 92 nv/hz f = 100 khz 4.4 nv/hz dc performance input offset voltage 25 80 v input offset voltage drift from ? 40c to + 85c 0.1 1.5 v/c from 25c to 85c 0.05 1 v/c input bias current at 25c 0.35 1.6 pa at 8 5c 8.5 30 pa input bias offset current at 25c 0.25 1.25 pa at 8 5c 0.4 pa open - loop gain v out = 1.5 v to 3.5 v 98 102 db input characteristics input resistance common mode 1 00 g? input capacitance common mode 2 pf differential mode 3 pf input common - mode voltage range cmrr > 80 db 0.5 3.8 v cmrr > 68 db 0 3.9 v common - mode rejection ratio v cm = 0.5v 88 94 db output characteristics output overdrive recovery time v out = v s 10% , positive/negative 60/50 ns output voltage swing g = +21, r f = 1 k? , r l open measured at fbx 1.15 to 3.46 0.86 to 3.66 v g = +21, r f = 100 k? , r l open measured at fbx 0.27 to 4.80 0.08 to 4.87 v linear output current v out = 1 v p - p, 60 db sfdr 10 ma rms short - circuit current sinking/sourcing 32/38 ma power supply operating range 3.3 12 v positive power supply rejection ratio 90 100 db negative power supply rejection ratio 86 100 db
ADA4350 data sheet rev. b | page 10 of 37 5 v internal switchi ng network and digital pins t a = 25c, +v s = 5 v, ? v s = 0 v , unless otherwise specified . see figure 1 for sampling and feedback switches position. table 7 . parameter symbol test conditions/comments min typ max unit feedback/sample analog switch analog signal range 0 5 v switch on resistance feedback r on, fb s0 to s2 , v cm = 2.5 v 308 390 ? t a = 85 c 382 ? s3 to s5 , v cm = 2.5 v 308 390 ? t a = 8 5c 384 ? sampling r on, s s6 to s8 , v cm = 2.5 v 6 10 770 ? t a = 8 5c 762 ? s9 to s11 , v cm = 2.5 v 612 770 ? t a = 8 5c 764 ? on - resistance match between channels feedback resistance r on, fb v cm = 2.5 v 3 21 ? sampling resistance r on, s v cm = 2.5 v 3 23 ? switch leakage currents sampling and feedback switch off leakage i s (off) 0.4 1. 2 pa t a = 85c 30 80 pa dynamic characteristics power - on time t on dvdd = 3.3 v 105 ns power - off time t off dvdd = 3.3 v 65 ns off isolation r l = 50 ? , f = 1 mhz feedback switches ?93 db sampling switches ?116 db channe l to channel crosstalk r l = 50 ? , f = 1 mhz ?83 db worst case switch f eedback capacitance (switch off ) c fb (off) 0.1 pf threshold voltages for digital input pins en, mode, dgnd, latch /p0, s clk/p1, sdo/p2, sdi/p3, cs /p4 1 input high voltage v ih dvdd = 5 v 2.0 v dvdd = 3.3 v 1.5 v input low voltage v il dvdd = 5 v 1.4 v dvdd = 3.3 v 1.0 v digital supplies dvdd, dgnd digital supply range 3.3 5.5 v qui e scent current e nabled 50 a d isabled 0.6 a +v s to dgnd h ead r oom 3.3 v 1 wh en referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specificat ion is listed. for full pin names of multifunction pins, refer to the pin configuration and function descript ions section.
data sheet ADA4350 rev. b | page 11 of 37 5 v adc driver t a = 25c, +v s = 5 v, ? v s = 0 v , unless otherwise specified . see figure 1 for the p1 and m1 amplifiers , r l = 1 k ? when differential, and r l = 500 ? when single - ended. table 8 . parameter test conditions/comments 1 min typ max unit dynamic performance ?3 db bandwidth when used differentially, v out = 0.1 v p -p 33 mhz when used differentially, v out = 2.0 v p -p 16 mhz when p1 is used, v out = 50 m v p - p 47 mhz when p1 is used, v out = 1 .0 v p -p 16 mhz when m1 is used, v out = 50 m v p -p 37 mhz when m1 is used, v out = 1.0 v p - p 18 mhz overdrive recovery time for p1, positive recovery/negative recovery 200/200 ns for m1, positive recovery/ negative recovery 140/120 ns slew rate when differentially used, v out = 2 v step 37 v/s when p1 or m1 is single - ended, v out = 1 v step 20 v/s settling time 0.1% when used differentially, v out = 2 v step 75 ns when p1 is used, v out = 1 v step 60 ns when m1 is used, v out = 1 v step 60 ns noise/distortion performance harmonic distortion (hd2/hd3) when used differentially, f c = 100 khz, v out = 1 v p -p ?117/?116 dbc when used differentially, f c = 1 mhz, v out = 1 v p -p ?80/?85 dbc when p1 is used, f c = 100 khz, v out = 500 m v p - p ?108/?115 dbc w hen p1 is used, f c = 1 mhz, v out = 500 m v p - p ?80/?83 dbc when m1 is used, f c = 100 khz, v out = 500 mv p - p ?103/?107 dbc when m1 is used, f c = 1 mhz, v out = 500 mv p - p ?75/?78 dbc referred to input (rti ) voltage noise for p1, f = 10 hz 60 nv/hz for p 1, f = 10 0 k hz 5.2 nv/hz referred to output (rto ) voltage noise for p1and m1, f = 10 hz , measured at v out 2 140 nv/hz for p1 and m 1, f = 100 khz , measured at v out 2 18 nv/hz input current noise f = 100 khz, referred to p1 1.1 pa/hz dc performance output offset voltage differential 0.15 0.75 mv input offset voltage drift differential 0.6 16 v/c output offset voltage single - ended, p1 only 60 275 v single - ended, m1 only 70 250 v input offset voltage drift single - ended, p1 only 0.1 5.9 v/c single - ended, m1 only 0.3 4.5 v/c input bias current p1 only at vin1 pin 60 230 na p1 only at rf1 pin 60 350 na m1 only at ref pin 60 200 na input offset current p1 only 60 270 n a open - loop gain p1 only , v out = 1.5 v to 3.5 v 94 100 db gain m1 only 1.99 1.9995 2.01 v/v gain error ? 0.5 + 0.5 % gain error drift 0.6 3.4 ppm/c
ADA4350 data sheet rev. b | page 12 of 37 parameter test conditions/comments 1 min typ max unit input characteristics input resistance vin1 and ref 200 m? input capacitance vin1 and ref 1.4 pf input common - mode voltage range 0 3.9 v common - mode rejection ratio for p1, v cm = 0.5 v 84 94 db output characteristics output voltage swing r l = no load, single - ended 0.15 to 4.85 0.125 to 4.875 v r l = 500 ? , single - ended 0.28 to 4.72 0.24 to 4.76 v output common - mode voltage range 0 3.9 v linear output current for p1or m1, v out = 1 v p - p, 60 db sfdr 4 ma rms differential output, v out = 1 v p - p, 60 db sfdr 10 ma rms short - circuit current for p1 or m1, sinking/sourcing 4 1/63 ma capacitive load drive when used differentially at each v out x , 30% overshoot, v o ut = 100 mv p - p 33 pf when p1/m1 is used, 30% overshoot, v o ut = 50 mv p -p 47 pf power supply operating range 3.3 12 v positive power supply rejection ratio for p1 86 104 db for m1 80 94 db negative power supply rejection ratio for p1 80 92 db for m1 76 88 db 1 p1 and m1 within this table refer to the amplifiers shown in figure 1 .
data sheet ADA4350 rev. b | page 13 of 37 timing specification s all input signals are specified with t r = t f = 2 ns (10% to 90% of dvdd) and timed from a voltage threshold level of v th = 1.3 v at dvdd = 3.3 v or v th =1.7 v at dvdd = 5 v. guaranteed by characterization; not production tested. see figure 2 and figure 3 . table 9 . dvdd = 3.3 v dvdd = 5 v parameter description 1 min max min max unit t 1 sclk period. 20 20 ns t 2 sclk positive pulse width. 10 10 ns t 3 sclk negative pulse width. 10 10 ns t 4 cs setup time. the time required to begin sampling data after cs goes low. 1 1 ns t 5 cs hold time. the amount of time required for cs to be held low after the last data bit is sampled before bringing cs high. data is latched on the cs rising edge. if latch is held low, data is also applied on the cs rising edge. 7 5 ns t 6 cs positive pulse width. the amount of time required between consecutive words. 2 1 ns t 7 data setup time. the amount of time the data bit (sdi) must be set before sampling on the falling edge of sclk. 1 1 ns t 8 data hold time. the amount of time sdi must be held after the falling edge of sclk for valid data to be sampled. 2 2 ns t 9 data latched to the internal switches updated. the amount of time it takes from the latched data being applied until the internal switches are updated. 145 140 ns latch disabled referenced from the rising edge of cs . latch enabled referenced from the falling edge of latch . t 10 latch negative pulse width. 3 3 ns t 11 2 sclk rising edge to sdo valid. the amount of time between the sclk rising edge and the valid sdo transitions (cl sdo 3 = 20 pf). 15 10 ns t 12 cs rising edge to the sclk falling edge. the amount of time required to prevent a 25 th sclk edge from being recognized (only 24 bits allowed for valid word). 1 1 ns 1 when referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specific ation is listed. for full pin names of multifunction pins, refer to the pin configuration and function descriptions section. 2 this is while in d aisy - chain mode and in readback mode. 3 cl sdo is the capacitive load on the sdo output. timing diagrams for serial mode t 4 t 5 t 2 t 8 t 7 t 1 t 9 t 9 t 10 t 6 sclk sdi 23 22 21 20 19 18 17 16 15 14 13 12 1 1 10 8 9 cs 7 6 5 4 3 2 0 1 interna l switches position switches upd a ted t 3 interna l switches position switches upd a ted la tch v th v th v th v th la tch enabled: l a tched d at a applied on f alling edge of l a tch la tch disabled: d at a l a tched and applied on rising edge of cs 12417-055 figure 2 . write operation
ADA4350 data sheet rev. b | page 14 of 37 t 6 t 12 t 1 1 v th v th v th v th cs sclk sdi 23 22 21 20 19 3 sdo 1 2 read command l a tched on rising edge of cs readback completed on rising edge of cs 0 no p command 23 22 21 20 19 4 3 1 2 0 4 read command: input word specifies register t o be read readback: selected register d at a clocked out 23 22 21 20 19 4 3 1 2 0 und e f i n e d la tch la tch disabled: d at a l a tched and applied on rising edge of cs 12417-056 figure 3 . read operation
data sheet ADA4350 rev. b | page 15 of 37 absolute maximum rat ings table 10. parameter rating analog supply voltage 14 v digital supply voltage 5.5 v power dissipation see figure 4 common - mode input voltage vs 0.3v differential input voltage 0.7 v input current (in - n, in - p, vin1, rf1 , and ref) 20 ma storage temperature range ? 65c to +125c operating temperature range ? 40 c to +8 5c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the w orst c ase conditions, that is, ja is specified for a device soldered in a circuit board for surface - mount packages. table 11 lists the ja for the ADA4350 . table 11 . thermal resistance package type ja unit 28- lead tssop 72.4 c/w maximum power dissip ation the maximum safe power dissipation for the ADA4350 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c, which is the gla ss transition temperature, the properties of the plastic change. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4350 . exceeding a junction temperature of 175 c for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the die due to the ADA4350 output load drive. the quiescent power dissipation is the voltage between the supply pins (v s ) multiplied by the quiescent current (i s ). p d = quiescent power + ( total drive power ? load power ) ( ) l out l out s s s d r v r v v i v p 2 2 ? ? ? ? ? ? ? ? ? + = ( ) ( ) l out s s d r v i v p 2 + + = 0 0.5 1.0 1.5 2.0 2.5 3.0 ?55 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 maximum power dissi pa tion (w) ambient temperaure (c) 28-lead tsso p t j = 150 c 12417-102 figure 4 . maximum power dissipation vs. ambient temperature for a 4- layer board esd caution
ADA4350 data sheet rev. b | page 16 of 37 pin configuration an d function descripti ons 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 rf1 vout1 fb5 fb2 fb3 fb4 swb_out s w a_out vout2 ref sdi/p3 cs/p4 dvdd fb1 fb0 in-n swb_in ?v s s w a_in in- p sdo/p2 sclk/p1 l a tch/p0 en +v s mode dgnd vin1 ADA4350 (not to scale) t o p view 12417-002 figure 5 . pin configuration table 12 . pin function descriptions pin no. mnemonic description 1 sw b_ out s witch group b (s3 to s5 and s9 to s11) output. 2 rf1 feedback r esistor for output differential amplifier. 3 vout1 differential amplifier output 1 . 4 fb5 feedback p in 5 for fet input amplifier . 5 fb4 feedback p in 4 for fet input amplifier . 6 fb3 feedback p in 3 for fet input amplifier . 7 fb2 feedback p in 2 for fet input amplifier . 8 fb1 feedback p in 1 for fet input amplifier . 9 fb0 feedback p in 0 for fet input amplifier . 10 in - n fet input amplifier inverting input . 11 in -p fet input amplifier non i nverting input . 12 sw a_in switch group a (s0 to s2 and s6 to s8 ) i nput . 13 sw b_in switch group b (s3 to s5 and s9 to s11) input . 14 ? v s analog negative supply . 15 + v s analog positive supply . 16 en enable pin . 17 mode mode pin . use this pin to switch between the spi interface and the parallel interface. 18 dgnd digital ground . 19 latch /p0 latch bit in the serial mode ( latch ). parallel data b it 0 in parallel mode (p0). 20 s clk /p1 digital clock in serial mode ( s clk). parallel data b it 1 in parallel mode (p1). 21 sdo /p2 serial data out in serial mode (sdo). parallel data b it 2 in parallel mode (p2). 22 sdi /p3 serial data in in serial mode (sdi). parallel data b it 3 in parallel mode (p3). 23 cs /p4 select bit in serial mode ( cs ). parallel data b it 4 in parallel mode (p4). 24 dvdd digital positive supply . 25 ref reference for the adc d river at m1. 26 vout2 differential amplifier output 2 . 27 sw a _out switch group a (s0 to s2 and s6 to s8) output . 28 vin1 differential amplifier noninverting input .
data sheet ADA4350 rev. b | page 17 of 37 typical performance characterisitics full system these plots are for the full system , which includes the fet input amplifier, the switching network , and the adc driver . u nless otherwise stated, r l = 1 k ? differential . for vs = 5 v, d vdd = + 5 v , and f or vs = +5 v (or 2.5 v ) , d vdd = + 3.3 v . ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) r f = 5k? v out = 200mv p-p g = ?5 v s = 5v v s = +5v 12417-004 figure 6. small signal frequency response for various supplies, see test circuit in figure 49 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) vs = 5v g = ?5 r f = 5k? v out = 2v p-p v out = 1v p-p v out = 200mv p-p 12417-005 figure 7. frequen cy response for various voltage outputs , see test circuit in figure 49 12417-206 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 output vo lt age (v) time (100ns/div) g = ?5 v out = 2v p-p r f = 5k v s = 5v v s = 2.5v figure 8. large signal step response, g = 5 for various su pplies ?120 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 0.001 0.01 0.1 1 5 frequenc y (mhz) dis t ortion (dbc) ti a gain = ?5, adc driver gain = +1 r f = 5k v out = 4v p-p v s = 5 v , hd2 v s = 5 v , hd3 v s = +5 v , hd3 v s = +5 v , hd2 12417-207 figure 9. harmo n ic d istortion vs. frequency for variou s supplies , see test circuit in figure 48 1 10 100 1000 input referred vo lt age noise (nv/ hz) frequenc y (hz) v s = 5v 1 10 100 1k 10k 100k 1m 10m 100m 12417-208 figure 10 . input referred voltage noise vs. frequency 0 10 20 30 40 50 60 0 2 4 6 8 10 12 ?40 ?20 0 20 40 60 80 supp l y current [digi t a l and al l disable] (a) supp l y current [enable and m1 disable] (ma) temper a ture (c) digi t a l enable v s = 5v al l disable m1 disable 12417-2 1 1 figure 11 . supply current vs. temperature at different modes
ADA4350 data sheet rev. b | page 18 of 37 ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 psrr (db) frequenc y (khz) +psrr ?psrr 100 10 1 0.1 v s = 5v 12417-012 figure 12 . psrr vs. frequency ?0.3 0 20 40 60 80 100 120 140 160 180 200 220 240 ?0.2 ?0.1 0 0.1 0.2 0.3 settling time (%) time (ns) v s = 5v v out = 4v p-p ti a gain = ?5, adc driver gain = +1 12417-318 figure 13 . 0.1% settling tim e , see test circuit in figure 49 0 100 200 300 400 500 600 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 swtich on resis t ance () common-mode vo lt age (v cm ) v s = 5 v sample switch a t 85c sample switch a t 25c feedback switch a t 25c feedback switch a t 85c 12417- 1 14 figure 14 . switch on - resistance vs. common - mode voltage at s witches for v arious temperature
data sheet ADA4350 rev. b | page 19 of 37 fet input amp lifier unless otherwise stated, r l = 1 k?. for vs = 5 v, dvdd = + 5 v , and f or vs = 2.5 v, dvdd = + 3.3 v . ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) v s = 5v v out = 100mv p-p g = +2 r f = 1k c f = 3pf g = ?5 r f = 5k g = +10 r f = 9k 12417-214 figure 15 . small signal frequency response for various gains, v s = 5 v , s ee test circuit diagram s in figure 50 and figure 51 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 9 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) v s = 5v v out = 100mv p-p g = +2 r f = 1k c f = 3pf g = ?5 r f = 5k g = +10 r f = 9k 12417-216 figure 16 . small signal frequency response for various gains, v s = 5 v , see test circuit diagram s in figure 50 and figure 51 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) v s = 5v v out = 2v p-p g = +2 r f = 1k, c f = 3pf g = ?5 r f = 5k g = +10 r f = 9k 12417-213 figure 17 . large signal frequency response for various gains, v s = 5 v , see test circuit diagram s in figure 50 and figure 51 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 0.1 1 10 100 normalized closed-loo p gain (db) frequenc y (mhz) v s = 5v v out = 1v p-p g = +2 r f = 1k c f = 3pf g = ?5 r f = 5k g = +10 r f = 9k 12417-215 figure 18 . large signal frequency response for various gains, v s = 5 v , see test circuit diagram s in figure 50 and figure 51 12417-217 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 output vo lt age (v) time (100ns/div) v s = 5v g = ?5 v out = 2v p-p v s = 2.5v figure 19 . large signal step response for v arious supplies, g = 5 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 settling time (%) time (10ns/div) v s = 5v v out = 2v ste p g = ?5 r f = 5k time = 10ns/div 12417- 1 18 figure 20 . 0.1% settling tim e
ADA4350 data sheet rev. b | page 20 of 37 ?120 ?115 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ? 40 0.001 0.01 0.1 1 10 distortion (dbc) frequency (mhz) v s = 5v g = ?5 v out = 2v p-p r l = 1k ? hd2 hd3 12417-219 figure 21. distortion (hd2/hd3) vs. frequency, g = ?5 1 10 100 1000 input referred vol t age noise (nv/ 12417-212 figure 22. input voltage noise input offset voltage (v) number of parts 40 30 20 10 0 ?40 ?20 0 20 40 ?30 ?10 10 30 50 v s = 5v 326 units x = ?0.88v = 13.58v 12417-122 figure 23. input offset voltage 0 20 40 60 80 100 120 140 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 number of parts input offset voltage drift (v/c) v s = 5v 640 units x = 0.1v/c = 0.25v/c 12417-124 figure 24. input offset voltage drift ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 ?20 0 20 40 60 80 100 120 140 phase (degrees) open-loop gain (db) frequency (hz) 1 10 100 1k 10k 100k 1m 10m 100m 1g 12417-125 gain phase figure 25. open-loop gain and phase vs. frequency ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 cmrr (db) frequency (hz) 100 1k 10k 100k 1m 10m v s = 5v 12417-126 figure 26. cmrr vs frequency
data sheet ADA4350 rev. b | page 21 of 37 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 1m 10m psrr (db) frequency (hz) v s = 5v ?psrr +psrr 12417-127 figure 27. psrr vs frequency ?6 ?4 ?2 0 2 4 6 inpu t and output voltage (v) time (100ns/div) v in 6 v out v s = 5v g = +6 r l = 1k ? 12417-030 figure 28. output over drive recovery when used as an amplifier
ADA4350 data sheet rev. b | page 22 of 37 adc driver unless stated otherwise, r l = 1 k differential, and r l = 500 when single-ended. for v s = 5 v, dvdd = +5 v, and for v s = +5 v (or 2.5 v), dvdd = +3.3 v. ?9 ?6 ?3 0 3 6 0.1 1 10 100 normalized magnitude (db) frequency (mhz) v s = 5v r f = 1k ? v out (single-ended) = 50mv p-p v out (differential) = 100mv p-p p1 gain = 1 single-ended output at vout1 single-ended output at vout2 differential 12417-034 figure 29. small signal frequency response, v s = 5 v ?9 ?6 ?3 0 3 0.1 1 10 100 normalized magnitude (db) frequency (mhz) differential 12417-230 single-ended output at vout1 single-ended output at vout2 v s = 5v r f = 1k ? v out (single-ended) = 1v p-p v out (differential) = 2v p-p p1 gain = 1 figure 30. large signal frequency response, v s = 5 v ?9 ?6 ?3 0 3 6 0.1 1 10 100 normalized magnitude (db) frequency (mhz) v s = 5v r f = 1k ? v out (single-ended) = 50mv p-p v out (differential) = 100mv p-p p1 gain = 1 single-ended output at vout1 single-ended output at vout2 differential 12417-036 figure 31. small signal frequency response, v s = 5 v ?9 ?6 ?3 0 3 0.1 1 10 100 normalized magnitude (db) frequency (mhz) differential 12417-232 v s = 5v r f = 1k ? v out (single-ended) = 1v p-p v out (differential) = 2v p-p p1 gain = 1 single-ended output at vout1 single-ended output at vout2 figure 32. large signal frequency response, v s =5 v ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 amplitude (v) time (100ns/div) v s = 5v g = +1 vout1 vout2 12417-134 figure 33. large signal step response (single-ended output), v s = 5 v ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 amplitude (v) time (100ns/div) v s = 5v g = +1 r l = 1k ? 12417-135 figure 34. large signal step response (differential output), v s = 5 v
data sheet ADA4350 rev. b | page 23 of 37 ?0.40 ?0.35 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 amplitude (v) time (100ns/div) v s = 2.5v g = +1 vout2 vout1 12417-235 figure 35. large signal step response (single-ended output), v s = 2.5 v ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 amplitude (v) time (100ns/div) v s = 2.5v g = +1 12417-137 figure 36. large signal step response (differential output), v s = 2.5 v ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ? 30 0.001 0.01 0.1 1 distortion (dbc) frequency (mhz) hd2, differential hd2, single-ended output at vout1 hd2, single-ended output at vout2 hd3, differential hd3, single-ended output at vout1 hd3, single-ended output at vout2 v s = 5v v out = 4v p-p differential, 2v p-p single-ended g = +1 5 12417-138 figure 37. harmonic distortion vs. frequency output offset voltage (v) number of parts ?400 ?300 ?200 ?100 0 100 ?350 ?250 ?150 ?50 50 150 40 30 20 10 0 35 25 15 5 12417-141 v s = 5v 326 units x = ?35.9v = 85.18v figure 38. differential output offset voltage 0 20 40 60 80 100 120 140 160 180 ?4.8 ?3.2 ?1.6 0 1.6 3.2 4.8 6.4 number of parts offset voltage drift (v/c) v s = 5v 640 units x = 0.51v/c = 1.37v/c 12417-237 figure 39. differential output offset voltage drift 0 10 20 30 40 50 60 ?200 ?170 ?140 ?110 ?80 ?50 ?20 10 40 70 100 number of parts offset voltage (v) 12417-241 v s = 5v 326 units for p1: x = ?11.87v = 37.1v for m1: x = 6.17v = 30.27v figure 40. single-ended output offset voltage
ADA4350 data sheet rev. b | page 24 of 37 number of p arts offset vo lt age drift (v/c) 0 20 40 60 80 100 120 140 160 180 ?2.6 ?2.0 ?1.4 ?0.8 ?0.2 0.4 1.0 1.6 2.2 2.8 v s = 5v 640 units for p1: x = ?0.06v/c = 0.54v/c for m1: x = ?0.22v/c = 0.4v/c 12417-239 figure 41 . single - e nded offset voltage drift ?1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 0.001 0.01 0.1 1 10 cmrr (db) frequenc y (mhz) v s = 5v v cm = 0.5v 12417-049 figure 42 . cmrr vs. fr e quency ?6 ?4 ?2 0 2 4 6 input and output vo lt age (v) time (100ns/div) v s = 5v g = +2 r f = 1k? r l = 500? v in 2 v out 12417-050 figure 43 . output overdrive recovery ( p1 o nly) ?6 ?4 ?2 0 2 4 6 input and output vo lt age (v) time (100ns/div) v s = 5v g = +2 r f = 1k? r l = 500? v out v in 2 12417-051 figure 44 . output overdrive recovery ( m1 o nly) ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) v s = 5v ?psrr +psrr 12417-139 figure 45 . psrr vs. frequency (p1 o nly)
data sheet ADA4350 rev. b | page 25 of 37 1 10 100 1k 10k 100k 1m 10m 100m 1 10 100 1000 input referred vo lt age noise (nv/ hz) frequenc y (hz) v s = 5v 12417-242 figure 46 . input referred voltage n oise vs . frequency , p1 o nly , see test circuit diagram in figure 52 1 10 100 1k 10k 100k 1m 10m 100m 1 10 100 1000 output referred vo lt age noise (nv/ hz) frequenc y (hz) v s = 5v 12417-243 figure 47 . output referred voltage n oise vs . frequency, p1 and m1 , see test circuit diagram in figure 53
ADA4350 data sheet rev. b | page 26 of 37 test circuits lpf function generator 1k ? 5k ? 1k ? 1k ? vout1 measure distortion with differential output vout2 differential gain = 1 adc driver fet amp g = ?5 p1 m1 825 ? 500 ? 12417-058 500 ? 500 ? figure 48. harmonic distortion for full system 1k ? 5k ? 1k ? 1k ? vout1 measure parameters at differential output vout2 differential gain = 1 adc driver fet amp g = ?5 p1 m1 825 ? 500 ? v in 12417-059 500 ? 500 ? figure 49. full system measurement for other parameters c f r f r l measure frequency response r g g = 1 + r f r g ac signal of difference frequency fet amp 12417-148 figure 50. frequency response for fet input amplifier, noninverting gain configuration c f r f measure frequency response r g g = ?r f r g fet amp ac signal of difference frequency 12417-149 figure 51. frequency response for fet input amplifier, inverting gain configuration g = +1 input referred noise v n = output noise measure output noise here p1 v n 12417-150 figure 52. input referred voltage noise for p1 measure output refered voltage noise here inside chip p1 m1 1k ? 500 ? 1k ? 12417-151 figure 53. output referred voltage noise for p1 and m1
data sheet ADA4350 rev. b | page 27 of 37 theory of operation kelvin switching te chniques traditional gain selectable amplifiers use analog switches in a feedback loop to connect discrete external resistors and capacitors to the inverting input by selecting the appropriate feedback path . this approach introduces several errors due to the nonideal nature of the analog switches in the loo p. for example, the on - resistance of the analog switch causes voltage and temperature dependent gain errors , while the leakage current causes offset errors, especially at high temperature. the kelvin switching technique solves this problem by introducing two switches in each gain selection loop, one to connect the transimpedance / op am p output to the feedback network , and the other to connect the feedback network output to the downstream components. figure 54 shows a programmab le gain transimpedance amplifier with kel vin switching. v out v1 v2 s2b high impedance load example s1b s2a s1a c f1 r f1 r l c f2 r f2 i pho t o 12417-103 notes 1. s1a, s1b, s2a, and s2b are the analog switches. r fx are the feedback resis t ors specific t o each transimpedance pa th. c fx are the feedback ca p aci t ors specific t o each transimpedance pa th. figure 54 . programmable gain transimpedance amplifier with kelvin switching although this technique requires using twice as many switches, the voltage ( vx ) in the center node is no longer switch dependent ; it is only dependent on the current across the selected resistor (s ee equation 1 through equation 3 ) . v o ut = ? i photo ( r f2 + r s1b ) (1) v1 = v o ut ( r f2 /( r f2 + r s1b )) (2) substituting equation 1 into equation 2, v1 = ? i photo r f2 (3) where: v out is the output of the first amplifier. i photo is the current from the photodiode . r f2 is the feedback resistor of transimpedance p ath 2 . r s1b is the switch resistance of the s1b switch. the switches shown on the right (s2a and s2b) in figure 54 only ha ve a small output impedance and contribute negligible error if the amplifier drives a high impedance load. in the case of the ada4 350 , the high impedance load is the integrated adc driver.
ADA4350 data sheet rev. b | page 28 of 37 applications informa tion c onfiguring the ada4 350 see the e va l - ADA4350ruz - p user guide for details on the basic configuration of the ada4 350, and how to use the evaluation board. for more details on configuring the adc driver in a different gain setting , see the ada4941 - 1 data sheet . the gain settings of the ada4 350 can be chosen via the spi interface or manually through a 5 - lead dip switch . selecting the transimpedance gain paths manu ally or t hrough the parallel inte rface in the manual mode (or parallel mode) , only five out of the six trans impedance paths can be accessed (fb0 to fb4). figure 55 shows the simplified schematics of the ada4 350 and the positions of fb0 to fb4. in this example , the first two feedback paths (fb 0 and fb1) are configured as two different transimpedance gain paths. to operate in manual mode or in parallel mode , set the en pin ( p in 16) and the mode pin ( p in 17) to l ogic 1. in this mode, pin 19 to pin 23 represent p0 through p4 , respectively. to sel ect one gain , set the corresponding px pin to logic 1, and set all other px pins to l ogic 0 . table 13 shows the relationship between the gain select switches (p0 through p4) and the gain path selected. setting more than one px pin to logic 1 results in connecting the selected gain paths in p arallel. table 13 . manual mode or parallel mode operation bit on switch closed gain path selected p0 s0 and s6 fb0 p1 s1 and s7 fb1 p2 s2 and s8 fb2 p3 s3 and s9 fb3 p4 s4 and s10 fb4 s electing the transimpedance gain paths thr ough the spi i nterface (serial mod e) for serial mode operation, set the en pin ( p in 16) to l ogic 1 and the mode pin (pin 17) to l ogic 0. in serial mode, pin 19 is latch , pin 20 is s clk, pin 21 is sdo, pin 22 is sdi , and pin 23 is cs . serial mode operation uses a 24 - bit command to configure each individual switch, s0 through s11, as well as additional options. table 14 shows the 2 4 - bit map used in serial mode operation. table 15 shows the example codes that select the various transimpedance gain paths. multifunction pin names may be referenced by their relevant function only. vout2 adc driver switching network fet am p s w a_out ref in- p s w a_in en mode fb2 fb1 l a tch/p0 sclk/p1 fb4 fb3 sdi/p3 cs/p4 vin1 rf1 swb_out vout1 spi inter f ace swb_in fb0 sdo/p2 fb5 in-n ADA4350 3 26 25 23 2 28 1 27 4 5 6 7 8 9 22 21 20 19 17 16 13 12 11 10 s0 s1 s2 s6 s7 s8 s3 s4 s5 s9 s10 s 1 1 m1 p1 r f0 c f0 r f1 c f1 12417-101 figure 55 . simplified schematic
data sheet ADA4350 rev. b | page 29 of 37 table 14. 24- bit map used in serial mode operation bit no. function default setting 0 s0 on/off control. write 1 to this bit to close switch s0. 0 1 s1 on/off control. write 1 to this bit to close switch s1. 0 2 s2 on/off control. write 1 to this bit to close switch s2. 0 3 s3 on/off control. write 1 to this bit to close switch s3. 0 4 s4 on/off control. write 1 to this bit to close switch s4. 0 5 s5 on/off control. write 1 to this bit to close switch s5. 0 6 s6 on/off control. write 1 to this bit to close switch s6. 0 7 s7 on/off control. write 1 to this bit to close switch s7. 0 8 s8 on/off control. write 1 to this bit to close switch s8. 0 9 s9 on/off control. write 1 to this bit to close switch s9. 0 10 s10 on/off control. write 1 to this bit to close switch s10. 0 11 s11 on/off control. write 1 to this bit to close switch s1 1. 0 12 reserved. set to logic low. 0 13 1 optional internal 1 pf feedback capacitor between the inverting input and the output of the amplifier. write 1 to this bit to turn the capacitor on. 0 14 disable the sdo pin. write 1 to this bit to disable the sdo pin. 0 15 disable the m1 amplifier. write 1 to this bit to disable the m1 amplifier. 0 16 reserved. set to logic low. 0 17 reserved. set to logic low. 0 18 reserved. set to logic low. 0 19 reserved. set to logic low. 0 20 reserved. set to logic low. 0 21 reserved. set to logic low. 0 22 reserved. set to logic low. 0 23 read/write bit. set to 1 to read and set to 0 to write. 0 1 the optional internal 1 pf feedback capacitor provides a quick and convenient way to compensate the tia when using a high value feedback resistor (>1 m? ) . table 15. serial mode operation command (h ex code for mat, b23b0 ) switch closed gain path selected 00 00 41 (msb s ide) s0 and s6 fb0 00 20 41 s0 and s6 fb0, optional internal feedback capacitor on 00 00 82 s1 and s7 fb1 00 01 04 s2 and s8 fb2 00 02 08 s3 and s9 fb3 00 04 10 s4 and s10 fb4 00 08 20 s5 and s11 fb5
ADA4350 data sheet rev. b | page 30 of 37 spice model the spice model only supports parallel mode operation. pin p5 enables p arallel mode and allow s full switching network functionality . the en and mode inputs are internally set to high and low, respectively, and are not accessible in this model. figure 56 shows the recommended symbol pins when creati ng the ada4 350 symbol in the spice simulator. ADA4350 u1 vout1 in_n in_ p vcc vee dvdd dgnd vout2 ref sw a_in swb_in la tch/p0 sclk/p1 sdo/p2 sdi/p3 cs/p4 p5 rf1 fb1 fb0 fb2 fb4 fb3 fb5 sw a_out swb_out vin1 3 26 12 9 10 1 1 15 14 24 18 8 7 6 5 4 27 1 28 2 13 19 20 21 22 23 25 12417-200 figure 56 . recommended symbol layout table 16 . model pin descriptions symbol pin model node pin no. mnemonic 1 n10 10 in_n 2 n11 11 in_p 3 vcc 15 vcc 4 vee 14 vee 5 vdd 24 dvdd 6 dgnd 18 dgnd 7 n12 12 swa_in 8 n13 13 swb_in 9 po 19 latch /p 0 10 p1 20 s clk/p1 11 p2 21 sdo/p2 12 p3 22 sdi/p3 13 p4 23 cs /p4 14 p5 not applicable p5 15 n25 25 ref 16 n26 26 vout2 17 n3 3 vout1 18 n2 2 rf1 19 n28 28 vin1 20 27 27 swa_out 21 1 1 swb_out 22 4 4 fb5 23 5 5 fb4 24 6 6 fb3 25 7 7 fb2 26 8 8 fb1 27 9 9 fb0
data sheet ADA4350 rev. b | page 31 of 37 ADA4350 u1 vout1 in_n in_ p vcc vee dvdd dgnd vout2 vout1 vout2 ref sw a_in swb_in la tch/p0 sclk/p1 sdo/p2 sdi/p3 cs/p4 p5 rf1 fb1 fb0 fb2 fb4 fb3 fb5 sw a_out swb_out vin1 3 26 12 9 10 1 1 15 14 24 18 8 7 6 5 4 27 1 28 2 13 19 20 21 22 23 25 12417-201 r1 1k c1 r2 3k c2 r3 10k c3 r4 30k c4 r5 100k c5 r6 300k c6 ac 1 0 slne (0 1m 1k 0 0) c pho t odiode i1 5 v1 ?5 v2 ?5 v3 figure 57 . spice schematic example to test basic functionality
ADA4350 data sheet rev. b | page 32 of 37 transimpedance amplifier design theory because its low input bias current minimizes the dc error at the preamp output, the ADA4350 works well in photodiode preamp applications. in addition, its high gain bandwidth product and low input capacitance maximizes the signal bandwidth of the photodiode preamp. figure 58 shows the transimpedance amplifier model of the ADA4350 . ? + v out v b c d c m c m ADA4350 r sh = 10 11 ? c s i photo c f r f 12417-157 figure 58. transimpedance amplifier model of the ADA4350 the basic transfer function in equation 4 describes the transimpedance gain of the photodiode preamp. ff f photo out rsc ri v ? ? ? 1 (4) where: i photo is the output current of the photodiode. r f is the feedback resistor. c f is the feedback capacitance. the signal bandwidth is 1/(r f c f ), as determined by equation 4. in general, set r f such that the maximum attainable output voltage corresponds to the maximum diode current, i photo , allowing the use of the full output swing. the signal bandwidth attainable with this preamp is a function of r f , the gain bandwidth product (f gbw ) of the amplifier, and the total capacitance at the amplifier summing junction, including c s and the amplifier input capacitance of c d and c m . r f and the total capacitance produce a pole with the loop frequency (f p ). f p = 1/2 r f c s (5) with the additional pole from the open-loop response of the amplifier, the two-pole system results in peaking and instability due to an insufficient phase margin (see gray lines for the noise gain and phase in figure 59). adding c f to the feedback loop creates a zero in the loop transmission that compensates for the effect of the input pole, which stabilizes the photodiode preamp design because of the increased phase margin (see the gray lines for the noise gain and phase in figure 60). it also sets the signal bandwidth, f z (see the i to v gain line for the signal gain in figure 60). the signal bandwidth and the zero frequency, f z , are determined by ff z cr f 2 1 ? (6) equating the zero frequency, f z , with the f x frequency maximizes the signal bandwidth with a 45 phase margin. calculate f x as follows because f x is the geometric mean of f p and f gbw : gbw p x fff ?? (7) by combining equation 5, equation 6, and equation 7, the c f value that produces f x is defined by gbw f s f fr c c ?? ? 2 (8) the frequency response in this case shows approximately 2 db peaking and 15% overshoot. doubling c f and cutting the bandwidth in half results in a flat frequency response with approximately 5% transient overshoot. log f log f f p g = 1 g = r 2 c 1 s f x f gbw open-loop gain phase () |a| (db) ?180 ?135 ?90 ?45 0 12417-158 figure 59. noise gain and phase bode plot of the transimpedance amplifier design without compensation
data sheet ADA4350 rev. b | page 33 of 37 open-loop gain f f p g = 1 f f x f gbw g = 1 + c s /c f f z f n i to v gain |a (s)| ?135 ?90 ?45 0 45 90 g = r f c s (s) 12417-159 phase () figure 60. signal and noise gain and phase of the transimpedance amplifier design with compensation the dominant output noise sources in the transimpedance amplifier design are the input voltage noise of the amplifier, v noise , and the resistor noise due to r f . the effect due to the current noise is negligible in comparison. the gray line in figure 60 shows the noise gain and phase over frequencies for the transimpedance amplifier. the noise bandwidth is at the f n frequency, and is calculated by ff s gbw n ccc f f /)( ? ? (9) table 17 shows the dominant noise sources (r f and v noise ) for the transimpedance amplifier when it has a 45 phase margin for the maximum bandwidth, and in this case, f z = f x = f n . table 17. rms noise contributions of transimpedance amplifier contributor expression r f 2 ??? nf fr4kt v noise ? ? n f dfm s noise f c 2cccc v ?? ??? ? 2
ADA4350 data sheet rev. b | page 34 of 37 r f0 c f0 t i a 100 i p h o t o c d = 91 p f t o 100 n f s0 s6 r f1 c f1 r f2 c f2 r f3 c f3 r f4 c f4 s1 s7 s2 s8 s3 s9 s4 s 1 0 12417 - 06 5 notes 1. r fx are the feedback resis t ors specific t o each transimpedance pa th. c fx are the feedback ca p aci t ors specific t o each transimpedance pa th. figure 61 . ada4 350 configured as a transimpe d ance amplifier with five different gains transimpedance gain amplifier performance figure 61 shows the ada4 350 configured as a transimpedance amplifier with five different gains. the photodiode sensor capacitance , c d , varie s from 91 pf to 100 nf to showcase the transimpedance gain performance at various frequency. figure 62 to figure 65 shows the transimpedance vs. frequency at differen t c d settings. note that the compensation capacitor s, c f0 to c f4 , correct for the inherent instability of the transimpedance configuration . capacitors chosen were such that the trans - impedance gain response compensate s for the maximum bandwidth and is close to havi ng a 45 phase margin. 0.01k 0.1k 1k 10k 100k 1m 0.1m 1m 10m 100m transimpedance (?) frequenc y (hz) r f0 = 1k r f1 = 3k r f2 = 10k r f3 = 30k r f4 = 100k c d = 91pf r f0 = 1k, c f0 = 15pf r f1 = 3k, c f1 = 6.8pf r f2 = 10k, c f2 = 3.3pf r f3 = 30k, c f3 = 2.2pf r f4 = 100k, c f4 = 1pf c d = 91pf 12417-166 figure 62 . transimpedance vs. frequency, c d = 91 pf transimpedance (?) frequenc y (hz) 10k 100k 1m 10m 100m 1k 10k 100k 1m 0.1k 0.01k r f0 = 1k, c f0 = 33pf r f1 = 3k, c f1 = 15pf r f2 = 10k, c f2 = 10pf r f3 = 30k, c f3 = 5.6pf r f4 = 100k, c f4 = 3.3pf c d = 1nf 12417-167 figure 63 . transimpedance vs. frequency, c d = 1 nf
data sheet ADA4350 rev. b | page 35 of 37 frequenc y (hz) transimpedance (?) 10k 100k 1m 10m 100m 1k 10k 100k 1m 0.1k 0.01k r f0 = 1k, c f0 = 100pf r f1 = 3k, c f1 = 56pf r f2 = 10k, c f2 = 33pf r f3 = 30k, c f3 = 18 pf r f4 = 100k, c f4 = 10pf c d = 10nf 12417-168 figure 64 . transimpedance vs. frequency, c d = 10 nf frequenc y (hz) transimpedance (?) 10k 100k 1m 10m 100m 1k 10k 100k 1m 0.1k 0.01k c d = 100nf r f0 = 1k, c f0 = 300pf r f1 = 3k, c f1 = 180pf r f2 = 10k, c f2 = 100pf r f3 = 30k, c f3 = 56pf r f4 = 100k, c f4 = 33pf 12417-169 figure 65 . transimpedance vs. frequency, c d = 100 nf the effect of low feedback resi stor r f x as the load of the transimpedance amplifier increases, excessive peaking in the frequency response can be observed when the r f x value is too small. this peaking can persist even when excessive c f x overcompensate s for it . figure 66 shows the ADA4350 configured with a photodiode capacitance value of 91 pf and a 1 k ? transimpedance load. figure 67 shows the normalized frequency response of this configuration. by decreasing r f from 500 ? to 68 ?, the peaking in the frequency response increases progressively. th e large peaking translates to a huge overshoot in the pulse response , which is an undesirable result . + ? c d = 91pf 1k? ti a *overcompens a tes v out r fx c fx * i pho t o 12417-066 figure 66 . transimpedance amplifier circuit ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 1 1 normalized gain (db) frequenc y (hz) c d = 91pf r fx = 250?, c fx = 33pf r fx = 125?, c fx =47pf r fx = 68?, c fx = 100pf 10k 100k 1m 100m 10m r fx = 500?, c fx = 20pf 12417-067 figure 67 . normali zed frequency response with d ecreasing r f (s ee figure 66) to mitigate this effect, use an additional snubber circuit at the output of the fet input amplifier , as shown in figure 68 . in this configuration, the feedback resistor (r f x ) is 68 ? , and the capacitance of the photodiode is 40 pf. + ? c d = 40pf 1k? r s c s ti a 68 100pf i pho t o 12417-068 figure 68 . snubber circuit added to mitigate peaking figure 69 shows the effect of various snubber circuit s clamping down the peaking. without the snubber circuit, there is 6 db of peaking when an overcompensated c f x of 100 pf is used. with t he snubber circuits, the bandwidth is restricted to approximately 10 mhz. to compromise between the peaking and the bandwidth, adjust the values of the snubber circuit. ?9 ?6 ?3 0 3 6 normalized gain (db) frequenc y (hz) 100k 1m 10m 100m no snubber r s = 10?, c s = 5.6nf r f = 68 c f = 100pf c d = 40pf r l = 1k r s = 10?,c s = 33nf 12417-069 r s = 10?, c s = 10nf figure 69 . eff ect of snubber circuits on the transimpedance frequency response (s ee figure 68 )
ADA4350 data sheet rev. b | page 36 of 37 using the t network to implement large feedback resistor values large feedback resistors (>1 m) can cause the two following issues in the transimpedance amplifier design: ? if the parasitic capacitance of the feedback resistor exceeds the optimal compensation value, it can significantly reduce the tia signal bandwidth. ? if the required compensation capacitance is too low (<1 pf), it is not practical to choose a feedback capacitor. the t network (the r fx , r2, and r1 resistors) maintains the transimpedance gain and signal bandwidth with a lower feedback resistor and a resistive gain network, as shown in figure 70. c fx z f r fx r l v out r1 r2 tia i photo 12417-268 figure 70. t network the relationship between the transimpedance v out /i photo and the t network resistors (r fx , r1, and r2) can be expressed as ? ? ? ? ? ? ? ? ????? f f photo out z r2 r1 r2 z i v 1 (10) where: v out is the output voltage of the tia. i photo is the input photodiode current. z f = r fx /(( r fx c fx ) s + 1), where r fx and c fx are the feedback resistor and capacitor, respectively, of any of the chosen transimpedance gain paths. r1 and r2 are the t network gain resistors. if z f >> r2, the transimpedance equation is simplified to ? ? ? ? ? ? ?? ?? ?? r1 r2 scr r i v fxfx x f photo out 1 1)( therefore, as compared to the standard tia design, the t network uses a feedback resistor value that is 1/(1 + r1/r2) smaller to obtain the same transimpedance. this eliminates the concern of the high parasitic capacitance associated with the large feedback resistor. to maintain the same signal bandwidth (or same pole), increase c f by a factor of 1 + r2/r1 to eliminate concerns of an impractical small compensation capacitor. as compared to a standard tia design, the t network is noisier because the dominant voltage noise density is amplified by the gain factor 1 + r2/r1. figure 71 shows the ADA4350 configured as a 1 m trans- impedance path and its t network equivalent. figure 72 compares the performance of the 1 m path and the equivalent t network with and without compensation capacitors. 3.3pf 100k ? 0.5pf 1m ? r l v out 111 ? 1k? tia i photo c d = 91pf 12417-269 figure 71. 1 m transimpedance path and its equivalent t network transimpedance ( ? ) frequency (hz) 10k 100k 1m 10m 10k 100k 1m 1k 10m v s = 5v, dv dd = +5v c d = 91pf r f = 1m ? 1m ? t network equivalent r f = 1m ? , c f = 500ff 1m ? t network equivalent, c f = 3.3pf 12417-070 figure 72. comparing the 1 m transimpedance path and t network performance
data sheet ADA4350 rev. b | page 37 of 37 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 73 . 28 - lead thin shrink small outline package [tssop] , (ru - 28) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADA4350aruz ?40c to +85c 28- lead thin shrink small outline package [tssop] ru -28 ADA4350aruz -r7 ?40c to +85c 28- lead thin shrink small outline package [tssop] ru -28 eval - ADA4350ru z -p evaluation board for 28 - lead tssop , precision version with guard rings 1 z = rohs compliant part. ? 2015 C 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12417 - 0- 3/16(b)

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